Question: Is it possible to use “assert” to stop the tool doing synthesis in a defined condition? If yes, when is it useful to use?

Answer: “assert” statement in VHDL is very beneficial for checking simulation conditions in certain times to give failure, error, warning of info about the testbench condition. But, is it possible to use “assert” statement in Synthesis? The answer is “Yes”. In Vivado, you can add your “assert” condition in architecture body part and if the condition does not met, the Synth will stop and give message that you wrote in the RTL with “failure” option. Do not forget to enable “assert” in Synthesis settings of Vivado. You can use this option if you want to limit the tool for synthesis of a module having AXI interface if it has more than 64-bit data width like the example code in the image. Or, you can calculate the actual baud rate according to the clock frequency in a UART transciever module and give warning if it is higher than some treshold value.

“𝑺𝒉𝒂𝒓𝒊𝒏𝒈 𝒌𝒏𝒐𝒘𝒍𝒆𝒅𝒈𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒆𝒇𝒇𝒊𝒄𝒊𝒆𝒏𝒕 𝒍𝒆𝒂𝒓𝒏𝒊𝒏𝒈 𝒎𝒆𝒕𝒉𝒐𝒅”