Our github account and the first repo is alive 🚀

We encourage digital design #FPGA, #SoC, #VHDL, #Verilog and #EmbeddedSystem enthusiastics to follow our #github account and contribute our upcoming repos if possible.

Our first project is simple but a fundamental project for FPGAs. This project involves parsing a packet coming via UART and communicating with the FPGA and the outside world upon completion of the process. We utilized VHDL testbench with TEXTIO package to read sim data and write the result.

We generated python scripts to create files including messages and checking the accuracy of the VHDL project. You can access the files from the link:

https://lnkd.in/d9HUmc4X