Company news, tech talks and the FPGA & VHDL KnowHow Series.https://www.anadologic.com/https://www.anadologic.com/anadologic-hardware-academy-intro/https://www.anadologic.com/anadologic-hardware-academy-intro/Practice FPGA and digital design questions for free, answer in your own words and get AI grading within seconds. A five-minute tour of the ANADOLOGIC Hardware Academy.Thu, 01 Oct 2026 00:00:00 GMThttps://www.anadologic.com/government-fund-for-onfi-4-2-flash-memory-controller/https://www.anadologic.com/government-fund-for-onfi-4-2-flash-memory-controller/We are proud to announce that ANADOLOGIC has received TÜBİTAK 1507 Government R&D Funding…Wed, 28 Jan 2026 00:00:00 GMThttps://www.anadologic.com/anadologic-at-take-off-istanbul-2025/https://www.anadologic.com/anadologic-at-take-off-istanbul-2025/We participated in Take Off Istanbul 2025, held on 10–11 December 2025 at İstanbul Fuar Merkezi, one of the region’s…Sun, 25 Jan 2026 00:00:00 GMThttps://www.anadologic.com/anadologic-tech-talk-3-usb-gecmisten-gunumuze-universal-serial-bus-by-mehmet-akif-sertkaya/https://www.anadologic.com/anadologic-tech-talk-3-usb-gecmisten-gunumuze-universal-serial-bus-by-mehmet-akif-sertkaya/Herkese selamlar, saygılar. Anadolic Tech Talk sunumlarının üçüncüsünde birlikteyiz. İlk iki sunumu Yusuf arkadaşımız yapmıştı. Gömülü sistemlerde Be Metal, Artos,…Wed, 21 Jan 2026 00:00:00 GMThttps://www.anadologic.com/anadologic-tech-talk-1-baremetal-ve-rtos-gomulu-yazilim-by-yusuf-gunan/https://www.anadologic.com/anadologic-tech-talk-1-baremetal-ve-rtos-gomulu-yazilim-by-yusuf-gunan/Herkese selamlar, saygılar. Anadolacık firması olarak ilk Tek adını verdiğimiz aslında teknik bir sunum hazırladı Yusuf arkadaşımız. İlkini gerçekleştiriyoruz. Bunu…Tue, 20 Jan 2026 00:00:00 GMThttps://www.anadologic.com/anadologic-tech-talk-2-rtos-ve-embedded-linux-uzerine-gomulu-yazilim-by-yusuf-gunan/https://www.anadologic.com/anadologic-tech-talk-2-rtos-ve-embedded-linux-uzerine-gomulu-yazilim-by-yusuf-gunan/Evet, herkese selamlar, saygılar. Anadolu Tek Talk 2. bölümde birlikteyiz. İlk bölümde bitiremediğimiz aslında sunumumuza devam edecek Yusuf arkadaşımız. Yusuf…Tue, 20 Jan 2026 00:00:00 GMThttps://www.anadologic.com/anadologic-grows-to-6-full-time-engineers/https://www.anadologic.com/anadologic-grows-to-6-full-time-engineers/We are excited to announce that Anadologic has grown its team to 6 full-time engineers as of July 2025! This…Thu, 02 Oct 2025 00:00:00 GMThttps://www.anadologic.com/fundamentals-of-fpga-vhdl-synthesis-online/https://www.anadologic.com/fundamentals-of-fpga-vhdl-synthesis-online/Eğitmen: Mehmet Burak Aykenar | Tarih: 28-29-30 Temmuz | Saat 19:30 – 22:00 | Yer: Online | Eğitmen: Mehmet Burak AykenarTue, 01 Jul 2025 00:00:00 GMThttps://www.anadologic.com/fundementalas-of-vhdl-synthesis-course-online/https://www.anadologic.com/fundementalas-of-vhdl-synthesis-course-online/Eğitmen: Mehmet Burak Aykenar | Tarih: 23-24-25 Haziran | Saat 19:30 – 22:00 | Yer: Online | Eğitmen: Mehmet Burak AykenarWed, 18 Jun 2025 00:00:00 GMThttps://www.anadologic.com/anadologic-odtu-ee-sunumu/https://www.anadologic.com/anadologic-odtu-ee-sunumu/Kurucumuz Mehmet Burak AYKENAR ODTÜ Elektrik-Elektronik Mühendisliği 4. Sınıf öğrencilerine seminer dersi kapsamında…Thu, 08 May 2025 00:00:00 GMThttps://www.anadologic.com/embembeedded-world-2025-startup-pitch/https://www.anadologic.com/embembeedded-world-2025-startup-pitch/🚀 Exciting news from Embedded World 2025! Our founder, Mehmet Burak Aykenar, delivered a startup pitch presentation at the exhibition.Tue, 25 Mar 2025 00:00:00 GMThttps://www.anadologic.com/anadologic-is-going-global/https://www.anadologic.com/anadologic-is-going-global/AnadoLogic is going global! 🌍✨ We are thrilled to announce our participation in Embedded World 2025 in Nuremberg, Germany! This…Fri, 07 Mar 2025 00:00:00 GMThttps://www.anadologic.com/anadologic-is-growing-with-its-4th-employee/https://www.anadologic.com/anadologic-is-growing-with-its-4th-employee/Meet Kerem Yalçınkaya, 4th employee of AnadoLogic. Kerem has an outstanding…Mon, 24 Feb 2025 00:00:00 GMThttps://www.anadologic.com/first-long-term-intern-of-anadologic/https://www.anadologic.com/first-long-term-intern-of-anadologic/Meet Mehmet Akif Sertkaya from Ankara Yıldırım Beyazıt Üniversitesi, first long term intern of ANADOLOGIC. Akif will be working with…Sat, 25 Jan 2025 00:00:00 GMThttps://www.anadologic.com/anadologic-is-now-a-member-of-saha-istanbul/https://www.anadologic.com/anadologic-is-now-a-member-of-saha-istanbul/Exciting News from AnadoLogic We are proud to announce that ANADOLOGIC has officially…Sat, 18 Jan 2025 00:00:00 GMThttps://www.anadologic.com/anadologic-received-1507-tubitak-sme-rd-start-up-support-program/https://www.anadologic.com/anadologic-received-1507-tubitak-sme-rd-start-up-support-program/We are glad to announce that our project proposal for “𝗚𝗶𝗴𝗮𝗯𝗶𝘁 𝗘𝘁𝗵𝗲𝗿𝗻𝗲𝘁 𝗠𝗔𝗖 𝗜𝗣” design is accepted…Wed, 08 Jan 2025 00:00:00 GMThttps://www.anadologic.com/first-intern-of-anadologic/https://www.anadologic.com/first-intern-of-anadologic/Meet Berk Muammer KUZU from OSTİM Teknik Üniversitesi, first intern of ANADOLOGIC. We were not very eager to employ an intern especially…Tue, 07 Jan 2025 00:00:00 GMThttps://www.anadologic.com/anadologic-joined-turkish-integrated-circuits-alliance-tica/https://www.anadologic.com/anadologic-joined-turkish-integrated-circuits-alliance-tica/As AnadoLogic we are proud to join Turkish Integrated Circuits Alliance, supported by imec…Wed, 25 Dec 2024 00:00:00 GMThttps://www.anadologic.com/new-agreement-with-sar-arge/https://www.anadologic.com/new-agreement-with-sar-arge/As AnadoLogic, we are excited to start working with SAR ARGE TEKNOLOJİ VE YAZILIM A.Ş.’s young and dynamic team on…Sat, 07 Dec 2024 00:00:00 GMThttps://www.anadologic.com/zynq-workshop-for-subu-students/https://www.anadologic.com/zynq-workshop-for-subu-students/We were gladful to deliver a one day AMD Zynq SoC workshop for SUBU university students. It is always amazing…Sat, 07 Dec 2024 00:00:00 GMThttps://www.anadologic.com/our-github-account-is-alive/https://www.anadologic.com/our-github-account-is-alive/Our github account and the first repo is alive 🚀 We encourage digital design,#FPGA, #SoC, #VHDL, #Verilog and #EmbeddedSystem…Mon, 02 Dec 2024 00:00:00 GMThttps://www.anadologic.com/number-00002-employee-of-anadologic/https://www.anadologic.com/number-00002-employee-of-anadologic/Meet Murat ALKAN, number 00002 employee of AnadoLogic, 00001 is Mehmet Burak Aykenar 😊 This handsome young guy…Sat, 23 Nov 2024 00:00:00 GMThttps://www.anadologic.com/our-first-office/https://www.anadologic.com/our-first-office/Having an office is another milestone for our company, which is accomplished finally at Ostim Teknopark Turuncu Bina, Ankara, Turkiye.…Mon, 28 Oct 2024 00:00:00 GMThttps://www.anadologic.com/roketsan-egitimi/https://www.anadologic.com/roketsan-egitimi/Yaklaşık 10 yıl boyunca çalışmaktan ve ülkemiz savunma sanayine hizmet etmekten büyük kıvanç duyduğum ülkemizin gurur kaynağı Roketsan’a …Wed, 23 Oct 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-10/https://www.anadologic.com/fpga-vhdl-knowhow-series-10/Subject: Introduction to Serial Gigabit Transceivers – FPGA implementation and testing of Aurora 8b10b protocol over SFP modules and fiber-op…Mon, 12 Aug 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-9/https://www.anadologic.com/fpga-vhdl-knowhow-series-9/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: VHDL allows utilization of variable types inside process, function or procedure. They are different than signals in many ways,…Mon, 12 Aug 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-8/https://www.anadologic.com/fpga-vhdl-knowhow-series-8/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in…Sun, 21 Jul 2024 00:00:00 GMThttps://www.anadologic.com/anadologic-visits-empa-electronics-ankara-office/https://www.anadologic.com/anadologic-visits-empa-electronics-ankara-office/As AnadoLogic company, I visited Empa Electronics Ankara office, which distributes AMD FPGAs and many other products…Mon, 15 Jul 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-6/https://www.anadologic.com/fpga-vhdl-knowhow-series-6/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can…Tue, 09 Jul 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-7/https://www.anadologic.com/fpga-vhdl-knowhow-series-7/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Does it differ to add parenthesis and group two operands to get more efficient adder structure in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫:…Tue, 09 Jul 2024 00:00:00 GMThttps://www.anadologic.com/2-4-eylul-ankara-fundamentals-of-vhdl-and-fpga-egitim-duyurusu/https://www.anadologic.com/2-4-eylul-ankara-fundamentals-of-vhdl-and-fpga-egitim-duyurusu/Anadologic firması olarak ilk eğitimimizi 2-3-4 Eylül tarihlerinde Ankara’da Ostimpark Otel’de düzenliyoruz! “Fundamentals of VHDL and FPGA” eğitimi FPGA mimarisinin…Wed, 03 Jul 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series/https://www.anadologic.com/fpga-vhdl-knowhow-series/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it a problem to add all numeric_std, std_logic_arith and std_logic_unsigned packages in a module? 𝐀𝐧𝐬𝐰𝐞𝐫: Both the std_logic_arith…Thu, 20 Jun 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-1/https://www.anadologic.com/fpga-vhdl-knowhow-series-1/Question: Is it possible to use “assert” to stop the tool doing synthesis in a defined condition? If yes, when…Thu, 20 Jun 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-3/https://www.anadologic.com/fpga-vhdl-knowhow-series-3/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: How can you assign integer literals (such as 24, 100, etc) to a std_logic_vector type signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫:…Thu, 20 Jun 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-4/https://www.anadologic.com/fpga-vhdl-knowhow-series-4/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If you…Thu, 20 Jun 2024 00:00:00 GMThttps://www.anadologic.com/fpga-vhdl-knowhow-series-5/https://www.anadologic.com/fpga-vhdl-knowhow-series-5/𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do…Thu, 20 Jun 2024 00:00:00 GMT