Open-ended hardware questions, answered in your own words. AI grades every answer and tells you why. What you get right comes back later, to prove it stuck.
Free account ·
sign-up takes about 20 seconds
Four stages,
one signal path.
Read a question, write what you know, get it graded, and see it again later. That is the whole loop.
- 01
Pick a track
Six tracks are open, from digital design fundamentals to multi-vendor ecosystems. Every question can be read without an account.
- 02
Answer in your own words
No multiple choice. Write the explanation the way you would give it to a colleague. Answering needs a free account.
- 03
AI grades it
Correct earns 100 XP, partially correct 50 XP, needs revision 0 XP. Every grade comes with written feedback.
- 04
It comes back
A concept you got right returns after 3 days, then 7 more, then 21 more, so you can check that it held.
Eight tracks.
Six open today.
Each open track has 4 modules and 40 questions over two cycles: 240 questions you can answer now. Bare-metal software and embedded Linux are next.
- U1Track 01
4 modules · 40 questions
- 1.1Boolean algebra & logic functions
- 1.2Combinational vs. sequential logic
- 1.3Setup and hold fundamentals
- 1.4Finite state machines
- U2Track 02
4 modules · 40 questions
- 2.1VHDL-93 / VHDL-2008
- 2.2Verilog-2001
- 2.3SystemVerilog for design
- 2.4SystemVerilog assertions (SVA)
- U3Track 03
4 modules · 40 questions
- 3.1Logic fabric & CLBs
- 3.2Dedicated memory blocks
- 3.3Arithmetic blocks
- 3.4Clock distribution networks
- U4Track 04
4 modules · 40 questions
- 4.1I/O standards & electrical specs
- 4.2Source-synchronous I/O primitives
- 4.3Multi-gigabit transceivers
- 4.4High-speed protocol integration
- U5Track 05
4 modules · 40 questions
- 5.1Core timing principles
- 5.2Constraints (SDC / XDC)
- 5.3Clock domain crossing (CDC)
- 5.4Timing closure methods
- U6Track 06
4 modules · 40 questions
- 6.1AMD: 7-Series to Versal
- 6.2Lattice low-power & edge
- 6.3Microchip PolarFire & RISC-V SoC
- 6.4Selection matrix & trade-offs
- U7 · DNPTrack 07
Bare-Metal Software Development & RTOS
Hard and soft cores, MMIO drivers and FreeRTOS.
- 7.1Processor subsystems & memory maps
- 7.2Bare-metal C/C++ drivers
- 7.3Interrupt controllers & timers
- 7.4FreeRTOS real-time architecture
Not populated yetComing soon - U8 · DNPTrack 08
Yocto-Based Embedded Linux & SoC Integration
PS-PL interconnects, device trees and BitBake layers.
- 8.1PS-PL interconnect & coherency
- 8.2Boot chain & bitstream loading
- 8.3Device tree architecture
- 8.4Yocto & PetaLinux BSP
Not populated yetComing soon - U7 · U8 · DNPTracks 07-08
- 07Bare-Metal Software Development & RTOS
- 08Yocto-Based Embedded Linux & SoC Integration
Not populated yetComing soon
Every answer gets
a grade and a reason.
Our AI reads what you wrote and grades it. Every grade has written feedback; when an answer falls short you also see what was missing and a model answer.
What you got right
comes back.
A concept you answered correctly returns after 3 days, then after 7 more, then after 21 more.
Free · 6 tracks · 240 questions
Your firstanswer awaits.
Start with Track 01, Digital Design Fundamentals. Read any question now; a free account takes about 20 seconds when you want to answer.