Trainings
Training Catalog
Proven programs delivered to leading defense and technology organizations, and tailored to your team’s level, tools and target devices. On-site or online.
From binary logic and VHDL fundamentals to static timing analysis, TCL scripting and fixed/floating point arithmetic, implemented on Vivado and an FPGA board.
Delivered toHAVELSAN · ASELSAN · BAYKAR · CEZERİ · YAPI İDİS · BYTECRAFT
View programA deeper dive into VHDL for digital design teams: advanced data types, reusable and parameterized structures, testbenches and a two-session hands-on design workshop.
Delivered toASELSAN
View programFPGA architecture and the detailed use of AMD Vivado: synthesis and place & route flows, static timing analysis and timing closure techniques.
Delivered toASELSAN
View programAMD Zynq SoC system design: PS/PL partitioning, AXI interfaces, custom AXI4 peripherals and DMA, with hands-on examples in Vivado and Vitis.
Delivered toTÜBİTAK BİLGEM · CEZERİ · BAYKAR · ROKETSAN · BYTECRAFT
View programZynq UltraScale+ MPSoC architecture (APU, RPU, GPU, VCU, DPU, PL) with hands-on Kria KV260 video pipelines, GStreamer and H.264/H.265 encoding.
Delivered toTÜBİTAK BİLGEM
View programThe Zynq SoC program built around AMD’s MicroBlaze soft processor: AXI peripherals, Ethernet, CAN, DMA and custom AXI4 IP in Vivado and Vitis.
Delivered toQUBITRIUM
View programThree days entirely on FPGA timing: static timing analysis, XDC/SDC constraints, clock domain crossing and RTL-level timing closure techniques.
Delivered toROKETSAN
View programNew ANADOLOGIC Hardware Academy
Open-ended FPGA, digital design and SoC questions, answered in your own words. AI grades every answer and tells you why, and what you get right comes back later to prove it stuck.
References
Tell us about your team, tools and project goals. We will put together a program built around them.
