From siliconto systems.

All 8 tracks

• U1Track 01

  FoundationalStart here20 hours · 4 modules · 40 questions

  Digital Design Fundamentals

  Combinational Logic, Sequential Storage, Setup/Hold Apertures, and FSMs

  Master core Boolean algebra, Karnaugh maps, combinational logic hazard elimination, setup/hold physical foundations, Moore/Mealy state machines, and hardware arithmetic.

  Summary & modulesModule details

  Master core Boolean algebra, Karnaugh maps, combinational logic hazard elimination, setup/hold physical foundations, Moore/Mealy state machines, and hardware arithmetic.

  1. 1.1

     Boolean Algebra & Logic Functions

  2. 1.2

     Combinational vs. Sequential Logic

  3. 1.3

     Setup and Hold Fundamentals

  4. 1.4

     Introduction to Finite State Machines

  NeedsBasic binary arithmetic · High-school algebra · Curiosity about physical transistors

  Open Track 01
• U2Track 02

  Advanced32 hours · 4 modules · 40 questions

  HDL Mastery (VHDL, Verilog & SystemVerilog)

  Strong Typing, Procedural Semantics, Interfaces, and Assertions

  Rigorous hardware description. Strong typing in VHDL-2008, race-free Verilog-2001, and advanced SystemVerilog assertions (SVA), interfaces, and modports.

  Summary & modulesModule details

  Rigorous hardware description. Strong typing in VHDL-2008, race-free Verilog-2001, and advanced SystemVerilog assertions (SVA), interfaces, and modports.

  1. 2.1

     VHDL (VHDL-93 / VHDL-2008)

  2. 2.2

     Verilog (Verilog-2001)

  3. 2.3

     SystemVerilog for Design

  4. 2.4

     SystemVerilog Assertions (SVA)

  NeedsTrack 01

  Open Track 02
• U3Track 03

  Advanced30 hours · 4 modules · 40 questions

  FPGA Fabric Architecture & Primitives

  Configurable Logic Blocks, Block RAM, DSP Slices, and Clock Buffers

  Deep dive into physical silicon resources: Configurable Logic Blocks (CLBs), 6-input LUT fracturing, Distributed RAM, True Dual-Port Block RAM, DSP48 slices, and MMCM/PLLs.

  Summary & modulesModule details

  Deep dive into physical silicon resources: Configurable Logic Blocks (CLBs), 6-input LUT fracturing, Distributed RAM, True Dual-Port Block RAM, DSP48 slices, and MMCM/PLLs.

  1. 3.1

     Logic Fabric & CLBs

  2. 3.2

     Dedicated Memory Blocks

  3. 3.3

     Arithmetic Blocks

  4. 3.4

     Clock Distribution Networks

  NeedsTrack 01Track 02

  Open Track 03
• U4Track 04

  Expert35 hours · 4 modules · 40 questions

  High-Speed I/O & Physical Interfaces

  Single-Ended/Differential Standards, ODT, IDELAY/ODELAY, and SerDes

  Single-ended and differential signaling (LVDS, SSTL), programmable on-die termination (ODT), IDELAY/ODELAY picosecond tap alignment, and Multi-Gigabit SerDes transceivers.

  Summary & modulesModule details

  Single-ended and differential signaling (LVDS, SSTL), programmable on-die termination (ODT), IDELAY/ODELAY picosecond tap alignment, and Multi-Gigabit SerDes transceivers.

  1. 4.1

     I/O Standards & Electrical Characteristics

  2. 4.2

     Source-Synchronous I/O Primitives

  3. 4.3

     Multi-Gigabit Transceivers (SerDes)

  4. 4.4

     High-Speed Protocol Integration

  NeedsTrack 03

  Open Track 04
• U5Track 05

  Expert32 hours · 4 modules · 40 questions

  Static Timing Analysis (STA) & Timing Closure

  Timing Paths, Slack Equations, SDC/XDC Constraints, and CDC

  Timing paths, Slack calculations (WNS, TNS), SDC/XDC constraint formulation, Clock Domain Crossing (CDC) metastability prevention, and timing closure methodologies.

  Summary & modulesModule details

  Timing paths, Slack calculations (WNS, TNS), SDC/XDC constraint formulation, Clock Domain Crossing (CDC) metastability prevention, and timing closure methodologies.

  1. 5.1

     Core Timing Principles

  2. 5.2

     Constraints Engineering (SDC / XDC)

  3. 5.3

     Clock Domain Crossing (CDC)

  4. 5.4

     Timing Closure Methodologies

  NeedsTrack 01Track 03

  Open Track 05
• U6Track 06

  Advanced28 hours · 4 modules · 40 questions

  Multi-Vendor Ecosystem Comparison

  AMD, Lattice, and Microchip Silicon Architectures & Toolchains

  Architectural trade-offs across AMD (7-Series, UltraScale+, Versal), Lattice (iCE40, ECP5, Certus-NX), and Microchip (PolarFire Flash-based radiation-tolerant FPGA).

  Summary & modulesModule details

  Architectural trade-offs across AMD (7-Series, UltraScale+, Versal), Lattice (iCE40, ECP5, Certus-NX), and Microchip (PolarFire Flash-based radiation-tolerant FPGA).

  1. 6.1

     AMD Silicon Architectures: 7-Series to Versal

  2. 6.2

     Lattice Ultra-Low Power & Edge Architectures

  3. 6.3

     Microchip PolarFire Flash-Based Architecture & RISC-V SoC

  4. 6.4

     Multi-Vendor Architectural Selection Matrix & Trade-offs

  NeedsTrack 03

  Open Track 06