Peripherals to be worked with during training:
XADC, AXI QSPI, AXI TIMER, AXI UARTLITE, AXI Uart 16550, AXI Interrupt Controller, AXI DMA, AXI VDMA, Memory Interface Generator (MIG 7-Series for DDR2/DDR3), TEST PATTERN GENERATOR (TPG), VGA, AXI IIC, ILA (Integrated Logic Analyzer), AXI GPIO, Custom AXI4 Peripherals
Trainee Profile:
– Engineers or candidate engineers, working or soon be working on AMD (XILINX) Microblaze SoC based systems
– Managers, HW design, SW design, test, system engineers etc. who work on Microblaze SoC based systems and want to get knowledgeable about Microblaze on system, HW and SW perspective
Trainer: Mehmet Burak AYKENAR
| DAY1 | DAY2 | DAY3 | DAY4 | DAY5 | |
|---|---|---|---|---|---|
| Morning | FPGA & Microblaze Intro AXI Protocol | AXI GPIO, XADC, AXI Timer, AXI Interrupt Controller | Integrated Logic Analyzer (ILA) | AXI DMA & AXI-Stream HW Design in Vivado | Creating Custom AXI4 Peripherals in Vivado |
| Lunch | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover |
| Afternoon | Vivado & Vitis Intro MIG, AXI Uartlite | AXI QSPI, AXI IIC | AXI Uart 16550, TPG & VGA | AXI DMA & AXI-Stream SW Design in Vivado | SW Examples for AXI4 Custom Peripherals |