- Program #4
- 5 Days
- On-site or Online
This training focuses on AMD Zynq SoC–based system design, with particular emphasis on the distinction between the Processing System (PS) and Programmable Logic (PL), AXI interfaces, and the development of AXI-compatible IP using both software and VHDL. It also includes practical examples implemented in Vivado and Vitis.
The course covers the software and hardware aspects of Zynq SoC–based designs, the separation and interaction between these domains, and the overall system design approach.
Program Schedule
| Day 1 | Day 2 | Day 3 | Day 4 | Day 5 | |
|---|---|---|---|---|---|
| Morning | Introduction to Zynq SoC System Architecture & AXI | PS Baremetal SW Design with ARM Cortex-A9 | Dual Core AMP & PL HW Design with Soft IPs in Vivado | Creating Custom AXI4 Peripherals in PL | DMA & HP AXI Slave Ports |
| Lunch | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover |
| Afternoon | Details of PS, PL and Interfaces for Zynq SoC | SW Profiling & Boot SW Examples | HW Export to Vitis SW Examples | SW Examples for AXI4 Custom Peripherals | HW & SW Examples for DMA |
Who Should Attend
- Engineers or candidate engineers working, or soon to be working, on AMD Zynq SoC-based systems.
- Managers, HW design, SW design, test and system engineers who work on Zynq SoC-based systems and want to become knowledgeable about Zynq from the system, HW and SW perspective.
Trainer
Previously Delivered To
Interested in this program for your team?
Every program can be tailored to your team’s level, tools and target devices, and delivered on-site or online.