Description
The subjects, example designs and codes provided in this training are specially prepared to accelerate your team on FPGA design with VHDL language. Starting from the fundamental FPGA and VHDL concepts to the advanced topics such as fixed/floating point arithmetic and detailed static timing analysis with real world examples and implementations on Vivado IDE and FPGA eval board. This training is not just a course, but you can think of it as a “know-how transfer”.
Trainee Profile
-Engineers or candidate engineers, working or soon be working on digital design and FPGA field
-Managers, HW design, SW design, test, system engineers etc. who work on FPGA-based systems and want to get knowledgable about digital design and FPGA field
Trainer
Mehmet Burak AYKENAR
