- Program #1
- 5 Days
- On-site or Online
The subjects, example designs and codes provided in this training are specially prepared to accelerate your team on FPGA design with VHDL. Starting from the fundamental FPGA and VHDL concepts to advanced topics such as fixed/floating point arithmetic and detailed static timing analysis, every topic is backed by real-world examples implemented on Vivado IDE and an FPGA evaluation board.
This training is not just a course, but you can think of it as a “know-how transfer”.
Program Schedule
| Day 1 | Day 2 | Day 3 | Day 4 | Day 5 | |
|---|---|---|---|---|---|
| Morning | Binary Logic Intro to VHDL | FPGA Architecture | Sequential Logic Finite State Machines | FPGA Configuration | FPGA Memories |
| Lunch | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover |
| Afternoon | VHDL Properties FPGA Primitives & Macros | Vivado IDE Combinational Logic | Static Timing Analysis | Verification Methods TCL Scripting | FPGA Arithmetic & DSP Fixed/Floating Point Arithmetic |
Who Should Attend
- Engineers or candidate engineers working, or soon to be working, on digital design and FPGA.
- Managers, HW design, SW design, test and system engineers who work on FPGA-based systems and want to become knowledgeable about digital design and FPGA.
Trainer
Previously Delivered To
Interested in this program for your team?
Every program can be tailored to your team’s level, tools and target devices, and delivered on-site or online.