First long term intern of ANADOLOGIC
Meet Mehmet Akif Sertkaya from Ankara Yıldırım Beyazıt Üniversitesi, first long term intern of ANADOLOGIC. Akif will be working with […]
Anadologic is Now a Member of SAHA Istanbul
Exciting News from AnadoLogic We are proud to announce that ANADOLOGIC has officially […]
ANADOLOGIC Received 1507 – Tubitak SME R&D Start-Up Support Program
We are glad to announce that our project proposal for “𝗚𝗶𝗴𝗮𝗯𝗶𝘁 𝗘𝘁𝗵𝗲𝗿𝗻𝗲𝘁 𝗠𝗔𝗖 𝗜𝗣” design is accepted […]
First Intern of ANADOLOGIC
Meet Berk Muammer KUZU from OSTİM Teknik Üniversitesi, first intern of ANADOLOGIC. We were not very eager to employ an intern especially a second-year student, but […]
ANADOLOGIC Joined Turkish Integrated Circuits Alliance (TICA)
As AnadoLogic we are proud to join Turkish Integrated Circuits Alliance, supported by imec […]
Zynq Workshop for SUBU Students
We were gladful to deliver a one day AMD Zynq SoC workshop for SUBU university students. It is always amazing […]
New Agreement with SAR ARGE
As AnadoLogic, we are excited to start working with SAR ARGE TEKNOLOJİ VE YAZILIM A.Ş.’s young and dynamic team on […]
Our GitHub Account is Alive!
Our github account and the first repo is alive 🚀 We encourage digital design,#FPGA, #SoC, #VHDL, #Verilog and #EmbeddedSystem […]
#00002 Employee of AnadoLogic
Meet Murat ALKAN, number 00002 employee of AnadoLogic, 00001 is Mehmet Burak Aykenar 😊 This handsome young guy […]
Our First Office!
Having an office is another milestone for our company, which is accomplished finally at Ostim Teknopark Turuncu Bina, Ankara, Turkiye. […]
Roketsan Eğitimi
Yaklaşık 10 yıl boyunca çalışmaktan ve ülkemiz savunma sanayine hizmet etmekten büyük kıvanç duyduğum ülkemizin gurur kaynağı Roketsan’a …
FPGA & VHDL KnowHow Series – 10
Subject: Introduction to Serial Gigabit Transceivers – FPGA implementation and testing of Aurora 8b10b protocol over SFP modules and fiber-op […]
FPGA & VHDL KnowHow Series – 9
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: VHDL allows utilization of variable types inside process, function or procedure. They are different than signals in many ways, […]
FPGA & VHDL KnowHow Series – 8
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in […]
Anadologic Visits Empa Electronics
As AnadoLogic company, I visited Empa Electronics Ankara office, which distributes AMD FPGAs and many other products […]
FPGA & VHDL KnowHow Series – 7
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Does it differ to add parenthesis and group two operands to get more efficient adder structure in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: […]
FPGA & VHDL KnowHow Series – 6
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can […]
2-4 Eylül Ankara “Fundamentals of VHDL and FPGA” Eğitim Duyurusu
Anadologic firması olarak ilk eğitimimizi 2-3-4 Eylül tarihlerinde Ankara’da Ostimpark Otel’de düzenliyoruz! “Fundamentals of VHDL and FPGA” eğitimi FPGA mimarisinin […]
FPGA & VHDL KnowHow Series – 5
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do […]
FPGA & VHDL KnowHow Series – 4
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If you […]