First long term intern of ANADOLOGIC

First long term intern of ANADOLOGIC

Jan 25, 20251 min read

Meet Mehmet Akif Sertkaya from Ankara Yıldırım Beyazıt Üniversitesi, first long term intern of ANADOLOGIC. Akif will be working with […]

Anadologic is Now a Member of SAHA Istanbul

Anadologic is Now a Member of SAHA Istanbul

Jan 18, 20251 min read

Exciting News from AnadoLogic We are proud to announce that ANADOLOGIC has officially […]

ANADOLOGIC Received 1507 - Tubitak SME R&D Start-Up Support Program

ANADOLOGIC Received 1507 – Tubitak SME R&D Start-Up Support Program

Jan 8, 20251 min read

We are glad to announce that our project proposal for “𝗚𝗶𝗴𝗮𝗯𝗶𝘁 𝗘𝘁𝗵𝗲𝗿𝗻𝗲𝘁 𝗠𝗔𝗖 𝗜𝗣” design is accepted […]

First Intern of ANADOLOGIC

First Intern of ANADOLOGIC

Jan 7, 20251 min read

Meet Berk Muammer KUZU from OSTİM Teknik Üniversitesi, first intern of ANADOLOGIC. We were not very eager to employ an intern especially a second-year student, but […]

ANADOLOGIC Joined Turkish Integrated Circuits Alliance (TICA)

ANADOLOGIC Joined Turkish Integrated Circuits Alliance (TICA)

Dec 25, 20241 min read

As AnadoLogic we are proud to join Turkish Integrated Circuits Alliance, supported by imec […]

Zynq Workshop for SUBU Students

Zynq Workshop for SUBU Students

Dec 7, 20241 min read

We were gladful to deliver a one day AMD Zynq SoC workshop for SUBU university students. It is always amazing […]

New Agreement with SAR ARGE

New Agreement with SAR ARGE

Dec 7, 20241 min read

As AnadoLogic, we are excited to start working with SAR ARGE TEKNOLOJİ VE YAZILIM A.Ş.’s young and dynamic team on […]

Anadolgic Github is Alive

Our GitHub Account is Alive!

Dec 2, 20241 min read

Our github account and the first repo is alive 🚀 We encourage digital design,#FPGA, #SoC, #VHDL, #Verilog and #EmbeddedSystem […]

Number 00002 Employee of AnadoLogic

#00002 Employee of AnadoLogic

Nov 23, 20241 min read

Meet Murat ALKAN, number 00002 employee of AnadoLogic, 00001 is Mehmet Burak Aykenar 😊 This handsome young guy […]

Anadologic First Office - Ostim Teknopark

Our First Office!

Oct 28, 20241 min read

Having an office is another milestone for our company, which is accomplished finally at Ostim Teknopark Turuncu Bina, Ankara, Turkiye. […]

Roketsan Eğitimi 2024 Ekim

Roketsan Eğitimi

Oct 23, 20242 min read

Yaklaşık 10 yıl boyunca çalışmaktan ve ülkemiz savunma sanayine hizmet etmekten büyük kıvanç duyduğum ülkemizin gurur kaynağı Roketsan’a …

FPGA & VHDL KnowHow Series – 10

FPGA & VHDL KnowHow Series – 10

Aug 12, 20247 min read

Subject: Introduction to Serial Gigabit Transceivers – FPGA implementation and testing of Aurora 8b10b protocol over SFP modules and fiber-op […]

FPGA & VHDL KnowHow Series – 9

FPGA & VHDL KnowHow Series – 9

Aug 12, 20244 min read

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: VHDL allows utilization of variable types inside process, function or procedure. They are different than signals in many ways, […]

FPGA & VHDL KnowHow Series – 8

FPGA & VHDL KnowHow Series – 8

Jul 21, 20243 min read

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in […]

Anadologic Visits Empa Electronics

Anadologic Visits Empa Electronics

Jul 15, 20241 min read

As AnadoLogic company, I visited Empa Electronics Ankara office, which distributes AMD FPGAs and many other products […]

FPGA & VHDL KnowHow Series – 7

FPGA & VHDL KnowHow Series – 7

Jul 9, 20243 min read

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Does it differ to add parenthesis and group two operands to get more efficient adder structure in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: […]

FPGA & VHDL KnowHow Series – 6

FPGA & VHDL KnowHow Series – 6

Jul 9, 20241 min read

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can […]

Eğitim Duyurusu - Fundamentals of VHDL and FPGA

2-4 Eylül Ankara “Fundamentals of VHDL and FPGA” Eğitim Duyurusu

Jul 3, 20242 min read

Anadologic firması olarak ilk eğitimimizi 2-3-4 Eylül tarihlerinde Ankara’da Ostimpark Otel’de düzenliyoruz! “Fundamentals of VHDL and FPGA” eğitimi FPGA mimarisinin […]

FPGA & VHDL KnowHow Series – 5

FPGA & VHDL KnowHow Series – 5

Jun 20, 20242 min read

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do […]

FPGA & VHDL KnowHow Series – 4

FPGA & VHDL KnowHow Series – 4

Jun 20, 20241 min read

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If you […]