Government Fund for ONFI 4.2 Flash Memory Controller
We are proud to announce that ANADOLOGIC has received TÜBİTAK 1507 Government R&D Funding…
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#SoC
Our GitHub Account is Alive!
Our github account and the first repo is alive 🚀 We encourage digital design,#FPGA, #SoC, #VHDL, #Verilog and #EmbeddedSystem…
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Our First Office!
Having an office is another milestone for our company, which is accomplished finally at Ostim Teknopark Turuncu Bina, Ankara, Turkiye.…
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Roketsan Eğitimi
Yaklaşık 10 yıl boyunca çalışmaktan ve ülkemiz savunma sanayine hizmet etmekten büyük kıvanç duyduğum ülkemizin gurur kaynağı Roketsan’a …
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FPGA & VHDL KnowHow Series – 10
Subject: Introduction to Serial Gigabit Transceivers – FPGA implementation and testing of Aurora 8b10b protocol over SFP modules and fiber-op…
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FPGA & VHDL KnowHow Series – 9
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: VHDL allows utilization of variable types inside process, function or procedure. They are different than signals in many ways,…
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FPGA & VHDL KnowHow Series – 8
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in…
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FPGA & VHDL KnowHow Series – 6
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can…
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FPGA & VHDL KnowHow Series – 7
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Does it differ to add parenthesis and group two operands to get more efficient adder structure in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫:…
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FPGA & VHDL KnowHow Series – 2
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it a problem to add all numeric_std, std_logic_arith and std_logic_unsigned packages in a module? 𝐀𝐧𝐬𝐰𝐞𝐫: Both the std_logic_arith…
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