𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋?

𝐀𝐧𝐬𝐰𝐞𝐫: If you assign two or more different values to a signal concurrently in VHDL this is called as “multi-driven net” such as:

𝑒_𝑜 <= 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟(𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑎_𝑖) + 𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑏_𝑖));
𝑒_𝑜 <= 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟(𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑎_𝑖) – 𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑏_𝑖));

This is not allowed and you will get this critical warning from Vivado:

[𝑆𝑦𝑛𝑡ℎ 8-6859] 𝑚𝑢𝑙𝑡𝑖-𝑑𝑟𝑖𝑣𝑒𝑛 𝑛𝑒𝑡 𝑜𝑛 𝑝𝑖𝑛 𝑏𝑙𝑎𝑏𝑙𝑎 𝑤𝑖𝑡ℎ 1𝑠𝑡 𝑑𝑟𝑖𝑣𝑒𝑟 𝑝𝑖𝑛 ‘𝑏𝑙𝑎𝑏𝑙𝑎_𝑓𝑖𝑟𝑠𝑡’ 𝑎𝑛𝑑 2𝑛𝑑 𝑑𝑟𝑖𝑣𝑒𝑟 𝑝𝑖𝑛 ‘𝑏𝑙𝑎𝑏𝑙𝑎_𝑠𝑒𝑐𝑜𝑛𝑑’

But if you assign the same value to a signal concurrently multiple time such as:

𝑒_𝑜 <= 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟(𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑎_𝑖) + 𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑏_𝑖));
𝑒_𝑜 <= 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟(𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑎_𝑖) + 𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(𝑏_𝑖));

Then synth tool such as Xilinx Vivado understands these two lines are actually the same and behaves them like there is one single assignment. Gives no warning at all.

In my opinion, it would be good to give an error for multi-driven net and at least give a warning about the second condition.

Please share your thoughts in comment section.

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