𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋?

𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do not want to use is an 𝐨𝐮𝐭𝐩𝐮𝐭 port, then it is OK to remove this port from instantiation or connect the port with “𝐨𝐩𝐞𝐧” keyword of VHDL:

𝑇𝐸𝑆𝑇_𝐼𝑁𝑆𝑇_𝐼 : 𝑒𝑛𝑡𝑖𝑡𝑦 𝑤𝑜𝑟𝑘.𝑡𝑒𝑠𝑡_𝑖𝑛𝑠𝑡(𝐵𝑒ℎ𝑎𝑣𝑖𝑜𝑟𝑎𝑙) 𝑝𝑜𝑟𝑡 𝑚𝑎𝑝 ( 𝑐𝑙𝑘    => 𝑐𝑙𝑘   , 𝑟𝑠𝑡    => 𝑟𝑠𝑡   , 𝑛𝑢𝑚1_𝑖   => 𝑛𝑢𝑚1_𝑖  , 𝑛𝑢𝑚2_𝑖   => 𝑛𝑢𝑚2_𝑖  , –𝑛𝑢𝑚_𝑠𝑢𝑏_𝑜 => 𝑜𝑝𝑒𝑛, 𝑛𝑢𝑚_𝑎𝑑𝑑_𝑜 => 𝑛𝑢𝑚_𝑎𝑑𝑑_𝑜 );

But, if the port you do not want to use is an 𝐢𝐧𝐩𝐮𝐭 port, then Vivado gives you an error. So, you have to connect some signal to an input port even a constant is OK.

For example, if we delete rst input port in the instantiation, then we get this error from Vivado:

𝑇𝐸𝑆𝑇_𝐼𝑁𝑆𝑇_𝐼 : 𝑒𝑛𝑡𝑖𝑡𝑦 𝑤𝑜𝑟𝑘.𝑡𝑒𝑠𝑡_𝑖𝑛𝑠𝑡(𝐵𝑒ℎ𝑎𝑣𝑖𝑜𝑟𝑎𝑙) 𝑝𝑜𝑟𝑡 𝑚𝑎𝑝 ( 𝑐𝑙𝑘    => 𝑐𝑙𝑘   , — 𝑟𝑠𝑡    => 𝑟𝑠𝑡   , 𝑛𝑢𝑚1_𝑖   => 𝑛𝑢𝑚1_𝑖  , 𝑛𝑢𝑚2_𝑖   => 𝑛𝑢𝑚2_𝑖  , –𝑛𝑢𝑚_𝑠𝑢𝑏_𝑜 => 𝑜𝑝𝑒𝑛, 𝑛𝑢𝑚_𝑎𝑑𝑑_𝑜 => 𝑛𝑢𝑚_𝑎𝑑𝑑_𝑜 );

[𝑆𝑦𝑛𝑡ℎ 8-2029] 𝑓𝑜𝑟𝑚𝑎𝑙 𝑟𝑠𝑡 ℎ𝑎𝑠 𝑛𝑜 𝑎𝑐𝑡𝑢𝑎𝑙 𝑜𝑟 𝑑𝑒𝑓𝑎𝑢𝑙𝑡 𝑣𝑎𝑙𝑢𝑒

I prefer to keep the output port and use “𝐨𝐩𝐞𝐧” keyword when I won’t plan to use that output port.

What about you? Please share your thoughts in comment section.

“𝑺𝒉𝒂𝒓𝒊𝒏𝒈 𝒌𝒏𝒐𝒘𝒍𝒆𝒅𝒈𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒆𝒇𝒇𝒊𝒄𝒊𝒆𝒏𝒕 𝒍𝒆𝒂𝒓𝒏𝒊𝒏𝒈 𝒎𝒆𝒕𝒉𝒐𝒅”