FPGA & VHDL KnowHow Series – 8

𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in Vivado?

𝐀𝐧𝐬𝐰𝐞𝐫: Some synthesis tools require you to write “clever” RTL code to help synthesis tool to allow resource sharing, so that you can get lower gate count for the circuit you design. What about Vivado, let’s see this with an example.

I will write 4 different codes having 4 32-bit integer inputs and 3 32-bit integer output. They all have the same functionality but orders and positions of the operands are different.

The first code is:

architecture RTL of RESSHARE is
begin

-- operands are brought together
P <= A + B + C;
Q <= A + B + D;
R <= C + D;

end RTL;

Here is the elaboration result of the Vivado for the code below:

FPGA & VHDL KnowHow Series - 8 - 1

We see 4 adders are shown in RTL elaboration. The synthesis result for this logic is 96 LUTs for an AMD 7-series FPGA.

The second code is:

architecture RTL of RESSHARE is
begin

-- operand orders are different!
P <= A + B + C;
Q <= D + A + B;
R <= C + D;

end RTL;

Here is the elaboration result of the Vivado for the code below:

FPGA & VHDL KnowHow Series - 8 - 2

We see 5 adders are shown in RTL elaboration for the second code block. So, let’s see the utilization after synthesis result for this circuit. Still it is 96 LUTs. Like in our previous know-how post, the elaboration and synthesis results are different. Again, relying on RTL elaboration results can produce wrong information about utilization or critical path analysis.

The third code is:

architecture RTL of RESSHARE is
begin

-- common signals are in different order
P <= A + B + C;
Q <= B + A + D;
R <= C + D;

end RTL;

Here is the elaboration result of the Vivado for the code below:

FPGA & VHDL KnowHow Series - 8 - 3

Same with the first code block results, also synthesis result is 96 LUTs again.

The fourth code is:

architecture RTL of RESSHARE is
begin

-- use intermediate terms to force resource sharing
process (A, B, C, D)
    variable T : integer;
begin
T := A + B;
P <= T + C;
Q <= T + D;
R <= C + D;
end process;

end RTL;

This time we used variable to implement the same functionality. Here is the elaboration result of the Vivado for the code below:

FPGA & VHDL KnowHow Series - 8 - 4

The result is same for both elaboration and synthesis.

To summarize, like in our previous post, we always need to check the synth results. Some synthesis tools in ASIC maybe pay critical attention to operand order but not Vivado.

“𝑺𝒉𝒂𝒓𝒊𝒏𝒈 𝒌𝒏𝒐𝒘𝒍𝒆𝒅𝒈𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒆𝒇𝒇𝒊𝒄𝒊𝒆𝒏𝒕 𝒍𝒆𝒂𝒓𝒏𝒊𝒏𝒈 𝒎𝒆𝒕𝒉𝒐𝒅”