FPGA & VHDL KnowHow Series – 6
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can […]
2-4 Eylül Ankara “Fundamentals of VHDL and FPGA” Eğitim Duyurusu
Anadologic firması olarak ilk eğitimimizi 2-3-4 Eylül tarihlerinde Ankara’da Ostimpark Otel’de düzenliyoruz! “Fundamentals of VHDL and FPGA” eğitimi FPGA mimarisinin […]
FPGA & VHDL KnowHow Series – 5
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do […]
FPGA & VHDL KnowHow Series – 4
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If you […]
FPGA & VHDL KnowHow Series – 3
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: How can you assign integer literals (such as 24, 100, etc) to a std_logic_vector type signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: […]
FPGA & VHDL KnowHow Series – 2
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it a problem to add all numeric_std, std_logic_arith and std_logic_unsigned packages in a module? 𝐀𝐧𝐬𝐰𝐞𝐫: Both the std_logic_arith […]
FPGA & VHDL KnowHow Series – 1
Question: Is it possible to use “assert” to stop the tool doing synthesis in a defined condition? If yes, when […]
ZYNQ SoC SYSTEM, HW & SW DESIGN
Description As the name of the training course implies, you will learn about the architecture, hardware implementation and software design […]
FPGA PROGRAMMING WITH VHDL
Description The subjects, example designs and codes provided in this training are specially prepared to accelerate your team on FPGA […]