𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: How can you assign integer literals (such as 24, 100, etc) to a std_logic_vector type signal in 𝐕𝐇𝐃𝐋?

𝐀𝐧𝐬𝐰𝐞𝐫: Assigning integer literals directly to std_logic_vector or unsigned type signals is not allowed and you will get this error from Vivado:

[𝑆𝑦𝑛𝑡ℎ 8-2774] 𝑡𝑦𝑝𝑒 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟 𝑑𝑜𝑒𝑠 𝑛𝑜𝑡 𝑚𝑎𝑡𝑐ℎ 𝑤𝑖𝑡ℎ 𝑡ℎ𝑒 𝑖𝑛𝑡𝑒𝑔𝑒𝑟 𝑙𝑖𝑡𝑒𝑟𝑎𝑙

[𝑆𝑦𝑛𝑡ℎ 8-2774] 𝑡𝑦𝑝𝑒 𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑 𝑑𝑜𝑒𝑠 𝑛𝑜𝑡 𝑚𝑎𝑡𝑐ℎ 𝑤𝑖𝑡ℎ 𝑡ℎ𝑒 𝑖𝑛𝑡𝑒𝑔𝑒𝑟 𝑙𝑖𝑡𝑒𝑟𝑎𝑙

You need conversion function defined in IEEE 𝐍𝐔𝐌𝐄𝐑𝐈𝐂_𝐒𝐓𝐃 package. You can assign an integer literal to a 𝐬𝐭𝐝_𝐥𝐨𝐠𝐢𝐜_𝐯𝐞𝐜𝐭𝐨𝐫 with “𝐭𝐨_𝐮𝐧𝐬𝐢𝐠𝐧𝐞𝐝” function and “𝐬𝐭𝐝_𝐥𝐨𝐠𝐢𝐜_𝐯𝐞𝐜𝐭𝐨𝐫” type conversion.

𝑠𝑖𝑔𝑛𝑎𝑙 𝑛𝑢𝑚_𝑜 : 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟 (7 𝑑𝑜𝑤𝑛𝑡𝑜 0); 𝑛𝑢𝑚_𝑜 <= 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟(𝑡𝑜_𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(255, 𝑛𝑢𝑚_𝑜’𝑙𝑒𝑛𝑔𝑡ℎ)); — 𝑛𝑢𝑚_𝑜 𝑔𝑒𝑡𝑠 𝑎𝑠𝑠𝑖𝑔𝑛𝑒𝑑 𝑡𝑜 255

But what if you try to assign an integer literal which is more than 8-bits? Then, Vivado trims the upper bits and assign only the lower 8-bits.

𝑠𝑖𝑔𝑛𝑎𝑙 𝑛𝑢𝑚_𝑜 : 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟 (7 𝑑𝑜𝑤𝑛𝑡𝑜 0); 𝑛𝑢𝑚_𝑜 <= 𝑠𝑡𝑑_𝑙𝑜𝑔𝑖𝑐_𝑣𝑒𝑐𝑡𝑜𝑟(𝑡𝑜_𝑢𝑛𝑠𝑖𝑔𝑛𝑒𝑑(511, 𝑛𝑢𝑚_𝑜’𝑙𝑒𝑛𝑔𝑡ℎ)); — 𝑛𝑢𝑚_𝑜 𝑔𝑒𝑡𝑠 𝑎𝑠𝑠𝑖𝑔𝑛𝑒𝑑 𝑡𝑜 255

What is your method to assign integer literals to 𝐬𝐭𝐝_𝐥𝐨𝐠𝐢𝐜_𝐯𝐞𝐜𝐭𝐨𝐫 types?

Please share your thoughts in comment section.

“𝑺𝒉𝒂𝒓𝒊𝒏𝒈 𝒌𝒏𝒐𝒘𝒍𝒆𝒅𝒈𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒆𝒇𝒇𝒊𝒄𝒊𝒆𝒏𝒕 𝒍𝒆𝒂𝒓𝒏𝒊𝒏𝒈 𝒎𝒆𝒕𝒉𝒐𝒅”