𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado?

𝐀𝐧𝐬𝐰𝐞𝐫: You can open synthesized netlist in Vivado schematics:

Vivado allows you to change LUT’s truth table property.

After you apply the change and save the change is applied in the constraint file automatically:

set_property INIT 4'hE [get_cells {result_o_OBUF[0]_inst_i_1}]

I have never used this property in any practical design. Synthesis tools are powerful and it is the digital designer’s job to write good RTL code and constraints to help the synthesis and P&R tool. However, this could be a good practice to show how logic is implemented and mapped into the LUTs in the FPGAs for educational purposes.

What about you? Please share your thoughts in comment section.

“𝑺𝒉𝒂𝒓𝒊𝒏𝒈 𝒌𝒏𝒐𝒘𝒍𝒆𝒅𝒈𝒆 𝒊𝒔 𝒕𝒉𝒆 𝒎𝒐𝒔𝒕 𝒆𝒇𝒇𝒊𝒄𝒊𝒆𝒏𝒕 𝒍𝒆𝒂𝒓𝒏𝒊𝒏𝒈 𝒎𝒆𝒕𝒉𝒐𝒅”