Advanced VHDL Design & Implementation

This five-day training program is designed for engineers who already work with VHDL and want to move on to advanced design techniques. After a short VHDL review, it covers the VHDL-2008 standard, static timing analysis and XDC/SDC timing constraints, I/O delays, generated clocks and clock domain crossing (CDC).

A full day is dedicated to a high-speed LVDS ADC/DAC interface example, where the timing topics of the previous days are applied to a real design. The last day covers floating-point and fixed-point arithmetic in FPGA, with fixed-point implementation examples.

Program Schedule

	Day 1	Day 2	Day 3	Day 4	Day 5
Morning	VHDL Review	Timing Paths Static Timing Analysis	I/O Delays Generated Clocks	High-Speed LVDS ADC/DAC Example	Floating-Point & Fixed-Point in FPGA
Lunch	Lunch & Recover	Lunch & Recover	Lunch & Recover	Lunch & Recover	Lunch & Recover
Afternoon	VHDL-2008	XDC/SDC Timing Constraints	Clock Domain Crossing (CDC)	High-Speed LVDS ADC/DAC Example	Fixed-Point Implementation Examples

Engineers or candidate engineers working on digital design and FPGA who want to learn more advanced subjects.
Managers, HW design, SW design, test and system engineers who work on FPGA-based systems and want to become more knowledgeable about digital design and FPGA with advanced design techniques.

Program Schedule

Who Should Attend

Trainer

Interested in this program for your team?