- Program #7
- 3 Days
- On-site or Online
This three-day training program was developed at ROKETSAN’s request and focuses entirely on FPGA timing topics: from digital timing concepts and timing paths to XDC/SDC constraints, clock domain crossing (CDC), and RTL-level as well as tool-level timing closure techniques in Vivado.
Program Schedule
| Day 1 | Day 2 | Day 3 | |
|---|---|---|---|
| Morning | FPGA Timing Overview Digital Timing Concepts | XDC/SDC Timing Constraints | RTL Level Timing Closure Techniques |
| Lunch | Lunch & Recover | Lunch & Recover | Lunch & Recover |
| Afternoon | Timing Paths Static Timing Analysis | Clock Domain Crossing (CDC) | Vivado Synthesis & Implementation Techniques |
Trainer
Previously Delivered To
Interested in this program for your team?
Every program can be tailored to your team’s level, tools and target devices, and delivered on-site or online.