- Program #2
- 5 Days
- On-site or Online
This five-day training program was designed at ASELSAN’s request for digital design teams seeking to develop a deeper understanding of VHDL. It shares many topics with Training Program #1, but differs significantly in the content covered on Day 3 and during the afternoon session of Day 4.
In the hands-on sessions, the VHDL concepts learned throughout the course are implemented and tested on an FPGA. Typically, after making a design decision together as a class, the design is developed collaboratively and interactively to demonstrate the practical implementation process.
Program Schedule
| Day 1 | Day 2 | Day 3 | Day 4 | Day 5 | |
|---|---|---|---|---|---|
| Morning | Binary Logic Intro to VHDL | FPGA Architecture | Advanced VHDL Data Types | Static Timing Analysis | Hands-On Design Workshop |
| Lunch | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover | Lunch & Recover |
| Afternoon | VHDL Constructs and Coding Principles FPGA Primitives & Macros | Combinational Logic Sequential Logic Finite State Machines | Reusable and Parameterized VHDL Structures | Testbench Development and VHDL Verification | Hands-On Design Workshop |
Trainer
Previously Delivered To
Interested in this program for your team?
Every program can be tailored to your team’s level, tools and target devices, and delivered on-site or online.