Fundamentals of FPGA Architecture & Design

This training focuses on FPGA architecture and the detailed use of AMD Vivado tools. It does not include an in-depth explanation of VHDL.

The program was developed in response to a specific request from ASELSAN and is delivered to ASELSAN.

Program Schedule

	Day 1	Day 2	Day 3
Morning	FPGA Architecture	Vivado Synthesis Flow	Vivado PaR Flow Timing Closure Techniques
Lunch	Lunch & Recover	Lunch & Recover	Lunch & Recover
Afternoon	FPGA Primitives & Macros VHDL Synthesis Constructs	Static Timing Analysis	Hands-On Workshop

Every program can be tailored to your team’s level, tools and target devices, and delivered on-site or online.