FPGA & VHDL KnowHow Series – 10
Subject: Introduction to Serial Gigabit Transceivers – FPGA implementation and testing of Aurora 8b10b protocol over SFP modules and fiber-op…
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FPGA & VHDL KnowHow Series
Short, practical answers to real FPGA and VHDL design questions.
FPGA & VHDL KnowHow Series – 9
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: VHDL allows utilization of variable types inside process, function or procedure. They are different than signals in many ways,…
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FPGA & VHDL KnowHow Series – 8
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in…
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FPGA & VHDL KnowHow Series – 6
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can…
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FPGA & VHDL KnowHow Series – 7
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Does it differ to add parenthesis and group two operands to get more efficient adder structure in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫:…
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FPGA & VHDL KnowHow Series – 2
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it a problem to add all numeric_std, std_logic_arith and std_logic_unsigned packages in a module? 𝐀𝐧𝐬𝐰𝐞𝐫: Both the std_logic_arith…
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FPGA & VHDL KnowHow Series – 1
Question: Is it possible to use “assert” to stop the tool doing synthesis in a defined condition? If yes, when…
Read moreFPGA & VHDL KnowHow Series – 3
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: How can you assign integer literals (such as 24, 100, etc) to a std_logic_vector type signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫:…
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FPGA & VHDL KnowHow Series – 4
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If you…
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FPGA & VHDL KnowHow Series – 5
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do…
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