FPGA & VHDL KnowHow Series – 9
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: VHDL allows utilization of variable types inside process, function or procedure. They are different than signals in many ways, […]
FPGA & VHDL KnowHow Series – 8
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it important orders and positions of the operands to allow resource sharing to get lower resource utilization in […]
Anadologic Visits Empa Electronics
As AnadoLogic company, I visited Empa Electronics Ankara office, which distributes AMD FPGAs and many other products […]
FPGA & VHDL KnowHow Series – 7
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Does it differ to add parenthesis and group two operands to get more efficient adder structure in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: […]
FPGA & VHDL KnowHow Series – 6
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens when you change truth table of a LUT in netlist after synthesis in Vivado? 𝐀𝐧𝐬𝐰𝐞𝐫: You can […]
2-4 Eylül Ankara “Fundamentals of VHDL and FPGA” Eğitim Duyurusu
Anadologic firması olarak ilk eğitimimizi 2-3-4 Eylül tarihlerinde Ankara’da Ostimpark Otel’de düzenliyoruz! “Fundamentals of VHDL and FPGA” eğitimi FPGA mimarisinin […]
FPGA & VHDL KnowHow Series – 5
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Can we delete or skip any port in instantiation of entities in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If the port you do […]
FPGA & VHDL KnowHow Series – 4
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: What happens if you assign multiple times the same value concurrently to a signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: If you […]
FPGA & VHDL KnowHow Series – 3
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: How can you assign integer literals (such as 24, 100, etc) to a std_logic_vector type signal in 𝐕𝐇𝐃𝐋? 𝐀𝐧𝐬𝐰𝐞𝐫: […]
FPGA & VHDL KnowHow Series – 2
𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧: Is it a problem to add all numeric_std, std_logic_arith and std_logic_unsigned packages in a module? 𝐀𝐧𝐬𝐰𝐞𝐫: Both the std_logic_arith […]